Infineon lists the CY7C1361B-117AJC as Obsolete. For existing BOM positions, this part is sourced through independent distribution channels.
9Mbit synchronous SRAM at 117 MHz
The CY7C1361B-117AJC is a 9Mbit synchronous SRAM organized as 256K x 36. It operates with a 117 MHz clock and delivers a 7.5 ns access time, which sets the read-to-data-valid window for the memory controller. The parallel memory interface and SDR (single data rate) technology mean data is transferred once per clock cycle. This suits applications where the controller and memory share a common bus clock and do not need DDR throughput.
The supply range is 3.135V to 3.6V, a standard 3.3V nominal rail with ±5% tolerance. Packaged in a 100-LQFP with a supplier device package of 100-TQFP (14x20). The 0.50 mm pitch LQFP footprint is common for mid-density SRAMs; the board layout should match the 14x20 mm body size.