9Mbit synchronous SRAM in 100-TQFP
The Infineon CY7C1361B-117AC is a 9Mbit synchronous SRAM organized as 256K x 36, clocked at 117 MHz with a 7.5 ns access time from clock rise. The parallel interface and pipelined SDR architecture target high-throughput data buffers in networking and telecom line cards. Housed in a 100-lead TQFP (14x20 mm body), the surface-mount package requires a 0.50 mm pitch layout with a central ground pad for thermal management.
Bus timing and memory organization
At 117 MHz the clock period is roughly 8.5 ns, and the 7.5 ns access time leaves about 1 ns of setup margin at the controller — tight enough that trace-length matching and signal-integrity simulation matter on a dense board. The 256K x 36 organization fills a 36-bit-wide data path without byte-lane stitching. Volatile SRAM with no refresh overhead means deterministic read latency, but the 0°C to 70°C temperature window limits deployment to equipment with active cooling or benign ambient conditions.
For a BOM line that requires this exact density and package, the only path is the spot market. A pin-compatible drop-in from a different vendor would need a full timing and signal-integrity revalidation — there is no listed second source.