9 Mbit synchronous SRAM — 100 MHz, 256K x 36
The CY7C1361B-100AC is a 9 Mbit synchronous SRAM organized as 256K x 36 bits, clocked at 100 MHz with a 8.5 ns access time. It uses a parallel memory interface and operates from a 3.135V to 3.6V supply. This is a volatile SRAM in the synchronous SDR (single data rate) family, typically used as a cache or data buffer in networking, telecom, and embedded systems where deterministic access latency matters more than density.
Housed in a 100-LQFP package with a 14x20 mm body (supplier device package 100-TQFP), the part is surface-mount and requires a reflow profile compatible with JEDEC moisture sensitivity level 3. The fine-pitch QFP footprint demands careful solder paste stencil design to avoid bridging.
Sourcing reality — obsolete, quoted to order
Infineon lists the CY7C1361B-100AC as Obsolete. No stock-holding claim is made — each order is sourced per request.