256K x 36 synchronous SRAM — 166 MHz pipeline
The CY7C1360B-166BGC is a 9Mbit synchronous SRAM organized as 256K words by 36 bits, clocked at 166 MHz with a 3.5 ns access time from the clock edge. The 36-bit data bus supports 32-bit data plus parity or ECC bits in a single burst, making it a natural fit for high-throughput data-path buffers in networking and telecom line cards. The parallel memory interface uses a standard synchronous pipeline — the address is latched on the rising clock edge, and the data appears after the programmed CAS latency.
No official successor or pin-compatible drop-in replacement is recorded from the original manufacturer. The part is sourced to order against an RFQ. A board-spin to a current-production synchronous SRAM (same package footprint, same supply rail) is the recommended long-term strategy.
Package and board-fit — 119-BGA
The 119-ball BGA measures 14 mm x 22 mm (supplier device package 119-PBGA). The 1.27 mm ball pitch is compatible with standard PCB fabrication tolerances, but the 119-ball array is non-standard — the land pattern must be verified against the official package outline drawing before committing the board layout. This restricts the part to indoor, temperature-controlled environments — not suitable for extended industrial or outdoor deployment without active thermal management.