The Cypress CY7C136-25JXI is a 16Kbit (organized 2K x 8) dual-port asynchronous SRAM that gives two independent systems — or two processor cores — simultaneous read/write access to the same memory array without external arbitration logic. The 25 ns access time means each port can complete a read or write cycle in 25 ns, which sets the bus timing margin for the shared memory window.
In a dual-port system, both ports can be active simultaneously; the part handles contention internally via its busy-logic handshake. If your system clock is 40 MHz (25 ns period), this SRAM matches one-cycle access at best, but you'll need to account for address-to-data setup and hold on both ports. For a 5V legacy bus, this part is a direct drop-in for older 16K dual-port designs.
Cypress no longer manufactures this device, and no last-time-buy window is open. New production is not available through the factory channel.
52-PLCC package — rework and board-fit notes
The part comes in a 52-lead PLCC with J-leads (52-LCC (J-Lead)), supplier device package 52-PLCC (19.13x19.13 mm). PLCCs are socket-friendly and reworkable with hot air — the J-lead bends inward, so the footprint has a smaller pad-to-pad pitch than a gull-wing QFP. The J-lead profile means less tombstoning risk than an SOIC, but you need a nozzle that covers the whole body evenly.