NoBL architecture — what it means for bus throughput
Standard synchronous SRAM inserts an idle cycle when switching from read to write (or write to read). The NoBL feature eliminates that turnaround penalty, sustaining full 100 MHz throughput on mixed-access patterns. If your design currently uses a pipelined synchronous SRAM that stalls on read-write transitions, this part recovers that lost bandwidth without changing the bus protocol.
