What this synchronous SRAM does in a system
The Infineon CY7C1355B-117AC is a 9 Mbit synchronous single-data-rate (SDR) SRAM organized as 256K words by 36 bits. It clocks at 117 MHz and delivers a 7 ns access time from clock edge to data valid.
117 MHz clock and 7 ns access — what they mean for bus timing
The 117 MHz clock sets the maximum rate at which the SRAM can accept new addresses. With a 7 ns access time, the data appears on the outputs within one clock cycle at full speed.
That means Infineon (formerly Cypress) no longer produces this exact order code, and there is no official last-time-buy window open. For a production BOM, this part is only available through the surplus and independent distribution channel — new-old-stock or pulled inventory. There is no pin-compatible direct replacement listed in the official records, so any substitution requires a board respin or a validated second-source qualification. If you are supporting an existing design that already uses this SRAM, the practical path is to source from independent stock while it lasts, or plan a migration to a current-generation synchronous SRAM or QDR/DDR variant in a similar package.
The part comes in a 100-pin LQFP with body dimensions 14x20 mm. It is a surface-mount package.