NoBL synchronous SRAM for high-throughput buffers
It clocks at 166 MHz with a 3.5 ns access time, eliminating the dead cycle between read and write operations that standard pipelined SRAMs require. The 36-bit word width suits designs needing parity or ECC alongside data — common in network switch buffers, telecom line cards, and DSP memory arrays. Supply range is 2.375 V to 2.625 V, and the part is specified for 0°C to 70°C commercial environments only.
The 166 MHz clock rate and 3.5 ns access time define the timing budget for the memory bus. NoBL architecture allows back-to-back read and write transactions without a turnaround cycle.