Synchronous SRAM for high-throughput parallel buses
The CY7C1352F-100AC is a synchronous SRAM organized as 256K x 18 bits (4.5 Mbit total), clocked at 100 MHz with a 4.5 ns access time. The 18-bit data bus suits systems needing parity or ECC alongside a 16-bit word — typical in networking buffers, DSP scratchpads, and cache tag stores where deterministic read-write latency matters.
Infineon lists the CY7C1352F-100AC as Obsolete. No official successor is named in the available records. For production runs that still require this exact footprint and timing, the only channel is the independent market — we source and quote against your BOM quantity. Confirm the date-code window and condition requirements before committing.
Package and temperature constraints for PCB fit
Housed in a 100-TQFP (14x20 mm) with 0.5 mm pitch. Supply voltage tolerance is 3.135V to 3.6V, so a 3.3V rail with ±5% regulation keeps the core within spec.