8 ns access, 100 MHz clock — synchronous SRAM for wide-word pipelines
The Cypress CY7C1338B-100AC is a 4 Mbit synchronous SRAM organized as 128K x 32 bits, with a single-cycle burst capability driven by a 100 MHz clock and an 8 ns access time. The synchronous SDR (single data rate) interface simplifies timing closure at the board level — the address and control signals are captured on the rising clock edge, so the bus controller only needs to manage setup and hold relative to that single edge.
Obsolete — last-time-buy and surplus sourcing
This part carries an official obsolete status. Cypress has discontinued the CY7C1338B-100AC, so new production through the original manufacturer is no longer available. For sustainment of existing designs — particularly in telecom infrastructure, industrial controllers, or test equipment that already has the 100-TQFP footprint laid out — the only supply channel is last-time-buy inventory or qualified surplus from independent distribution. No direct replacement part number has been assigned by Cypress for this specific speed and package variant, so any pin-compatible alternative must be validated against the 8 ns access time and 100 MHz clock requirements.
100-TQFP footprint and supply rails
The CY7C1338B-100AC is supplied in a 100-TQFP package with a 14x20 mm body. The supply voltage range is 3.15 V to 3.6 V, which aligns with a nominal 3.3 V rail — no additional regulator needed if the board already runs 3.3 V. The parallel memory interface uses standard SRAM control signals (chip enable, output enable, write enable, and burst control), so it integrates directly with most 32-bit bus masters without glue logic.