18 Mbit DDR II SRAM at 250 MHz
The Infineon CY7C1320KV18-250BZCT is a 18 Mbit synchronous SRAM organized as 512K x 36, clocked at 250 MHz on a parallel interface. This is a DDR II (Double Data Rate II) part — data transfers on both clock edges, so the effective bandwidth at 250 MHz is 500 MT/s per pin. The 36-bit word width suits high-throughput data paths like network packet buffers or cache tag arrays where a single chip provides both data and parity/ECC bits.
Supply rails and temperature envelope
Core supply range is 1.7 V to 1.9 V — a tight 200 mV window that demands a clean rail from a low-noise regulator.
165-ball FBGA footprint
Housed in a 165-ball LBGA (supplier device package 165-FBGA, 13x15 mm). The Tape & Reel packaging means the part ships on 13-inch reels for automated pick-and-place; the reel quantity is confirmed at quote time.
Infineon lists this part as Obsolete. For existing BOM lines, the supply path runs through independent distribution — surplus and new-old-stock inventory. Availability and pricing are lot-specific and confirmed against an RFQ.