52-PLCC dual-port SRAM — what the scorch mark tells you
The CY7C131A-15JXI is an 8Kbit dual-port asynchronous SRAM in a 52-lead PLCC (J-Lead) package — the kind of part you find on legacy controller boards where two bus masters need to swap data without wait states. The 15 ns access time means it can keep up with a 33 MHz bus without inserting dead cycles, which is why these still show up on repair benches: when the dual-port chip dies, the board hangs on arbitration.
Footprint and supply rails — board-fit checklist
The 52-PLCC (19.13 x 19.13 mm) footprint is a JEDEC-standard body — the J-Lead profile sits flush on the board with a 0.050-inch pitch, so a legacy PLCC socket or a direct-solder rework profile works.
Obsolete — sourcing reality for the BOM line
Infineon lists the CY7C131A-15JXI as obsolete. If you are repairing a board that uses this dual-port SRAM, the 52-PLCC footprint is the constraint; a pin-compatible replacement from the same family would need the same JEDEC outline and 5 V supply.