QDR II SRAM at 167 MHz — 18 Mbit in a 512K x 36 configuration
The CY7C1314BV18-167BZI is a 18 Mbit synchronous QDR II SRAM organized 512K x 36, clocked at 167 MHz. The QDR (Quad Data Rate) architecture delivers two read and two write data words per clock cycle — at 167 MHz the interface sustains a peak bandwidth of 12 Gbit/s across the 36-bit data bus. The 1.7 V to 1.9 V core supply keeps I/O levels compatible with 1.8 V logic families.
Industrial temperature range and package
The tray packaging means the parts are delivered in antistatic trays, not tape-and-reel; plan for pick-and-place with a tray feeder or a tube-to-tape conversion if the line is set up for reels.
Infineon lists the CY7C1314BV18-167BZI as Obsolete. For a BOM that already uses this density and package, the procurement path is to source from the spot market; there is no pin-compatible drop-in from Infineon's current QDR portfolio that matches the 165-FBGA footprint and 1.8 V supply without a board spin.