QDR II SRAM — 18 Mbit at 250 MHz
The CY7C1313CV18-250BZI is a 18 Mbit QDR II (Quad Data Rate) synchronous SRAM organized as 1M x 18 bits, clocked at 250 MHz. QDR II architecture delivers four data words per clock cycle — two read and two write — effectively quadrupling the data bandwidth of a conventional single-data-rate SRAM at the same clock frequency.
The 165-LBGA footprint requires a multi-layer PCB with controlled-impedance traces for the QDR II bus — the 250 MHz clock rate demands careful signal-integrity design on the read/write data paths. Supplied in tray packaging, it is ready for pick-and-place assembly without reel-to-reel transfer. The FBGA package is moisture-sensitive; verify the MSL level on the lot certificate before the reflow profile is set.
No official successor or pin-compatible replacement is listed on the manufacturer's lifecycle record. This part is not recommended for new designs. For existing BOM lines, the part is sourced through independent distribution — quantities are lot-specific and confirmed at RFQ. The 250 MHz QDR II interface and 1.8V supply rail are the primary constraints for any functional replacement; a board spin is likely required to migrate to a different SRAM family.