It clocks at 550 MHz on the parallel interface, delivering back-to-back read and write transactions on every rising and falling edge — no dead cycles between bus turns.
At 550 MHz the QDR II+ interface delivers a peak data rate of 1.1 G transfers per second per I/O pin (double-data-rate on both read and write ports). The 18-bit-wide data bus yields a theoretical bandwidth of 19.8 Gbit/s. In practice, signal-integrity margin on the 165-ball FBGA layout — trace length matching, on-die termination, and decoupling at the 1.7V–1.9V core supply — determines whether that rate closes timing in a real board.
Obsolete — last-time-buy and sourcing reality
Infineon (formerly Cypress) has discontinued this density and speed grade in the QDR II+ family. If a form-fit-function replacement is needed, a cross-reference search against other 36Mbit QDR II+ SRAMs in the 165-FBGA footprint is the next step, but no pin-compatible alternate is documented here.