10 ns asynchronous SRAM for tight bus timing
It uses a parallel interface, so the controller gets deterministic, single-cycle reads without the protocol overhead of serial memory — essential for cache, frame buffers, or any real-time data path where wait states cost throughput. The 10 ns access time means it can keep up with a 100 MHz bus clock if the controller's output-hold timing allows, but the real margin shows up at 66 MHz and below, where you can skip the pipeline stage.
Industrial temperature grade — outdoor and factory use
The supply range of 2.2V to 3.6V covers both 3.3V and 2.5V rails, so it can sit on a mixed-voltage board without a separate regulator for the memory bank.
Package and footprint: 54-TSOP II
Housed in a 54-TSOP II (0.400", 10.16mm width) surface-mount package. The shipping medium is Tray, not Tape & Reel, so plan for pick-and-place feeder changeover if your line is set up for reels.
Lifecycle: active, no last-time-buy pressure
The base product number is CY7C1061; the suffix GE30-10ZSXI identifies the 10 ns speed grade, industrial temperature, and TSOP II package.