10 ns asynchronous SRAM in 60-ball BGA
The CY7C1061AV33-10BAC is a 16Mbit asynchronous SRAM organized as 1M x 16, with a 10 ns access time that sets the minimum read/write cycle window for the memory bus. The 3V–3.6V supply range and 60-TFBGA (8x20 mm) package target board-level designs where a 16-bit wide data path and fast random access are required.
Parametric deep-dive — access time and organization
The 1M x 16 organization maps directly to a 16-bit microcontroller or DSP external bus without byte-lane muxing. Write cycle time matches the read access at 10 ns, so back-to-back writes at the same address are limited only by the bus turn-around.
Obsolete — sourcing through distribution
Infineon lists the CY7C1061AV33-10BAC as Obsolete. No new production runs are planned. The part is available only through franchised or independent excess inventory. We source per RFQ — confirm the BOM quantity and target lead time, and we will locate available stock across our supply network. The base product number CY7C1061 may have active or NRND siblings in the same package and speed grade; check the Infineon product selector for a drop-in replacement if the BOM can tolerate a different top-side marking.