For a 50 MHz bus with a 20 ns period, that leaves 10 ns for address setup, hold, and propagation delay through the board trace — tight but workable with controlled impedance and matched trace lengths. If the host controller has a 15 ns or 20 ns access-time requirement, this part meets it with margin; a 8 ns or 7 ns requirement would push the timing closure and may need a faster SRAM.
The 2.2V to 3.6V supply range allows this SRAM to sit on a 3.3V bus with 300 mV of headroom below the absolute maximum, or on a 2.5V rail with 300 mV margin above the minimum. The write cycle time matches the read access at 10 ns, so back-to-back writes at the same speed are supported without dead cycles.