16 Mbit async SRAM — 10 ns access, 1M x 16 bus
The Cypress CY7C10612G30-10ZSXIT is a 16 Mbit asynchronous SRAM organized as 1M x 16 bits, with a 10 ns access time.
10 ns access time — what it means for bus timing
The 1M x 16 organization matches a 16-bit data bus directly, eliminating the need for byte-lane muxing that a x8 part would require. Write cycle time is also 10 ns, so back-to-back writes keep the pipeline full.
