10 ns asynchronous SRAM in a 44-TSOP II footprint
The Infineon (formerly Cypress) CY7C1041G30-10ZSXIT is a 4 Mbit asynchronous SRAM organized as 256K words by 16 bits. The 10 ns access time targets high-speed cache, communications buffers, and industrial control systems where deterministic read/write latency matters.
Supply range and bus compatibility
At 3.3 V it interfaces directly with common FPGAs, MCUs, and DSPs; at 2.5 V it matches low-power logic families. The 10 ns write cycle time matches the read access time, so back-to-back read-write sequences run at full bus speed without dead cycles.