10 ns asynchronous SRAM — 4 Mbit in a 44-TSOP II
Packaged in a 44-TSOP II (10.16 mm wide), it is a surface-mount part intended for high-speed cacheless memory in 5 V logic systems — think legacy DSP boards, telecom line cards, or industrial controllers that still run a 5 V bus.
10 ns access — bus timing headroom
For a 5 V CPLD or DSP running at 50 MHz to 66 MHz, this gives enough margin to avoid wait-state insertion on back-to-back reads. If your processor's memory controller has a setup/hold window narrower than 2 ns, budget a series resistor on the data lines to damp reflections — the 44-TSOP II leadframe is not impedance-controlled.
Industrial temperature grade — where it goes
The 5 V supply rail is common in those environments — many legacy backplanes still distribute 5 V, and a local LDO would add cost. If your design lives in a climate-controlled server room, the commercial-grade sibling (CY7C1041D-10ZSXI) saves a few cents, but the industrial part gives you a single BOM for both indoor and outdoor variants.
No new factory orders are accepted; the only available stock sits in independent distribution channels.