1 Mbit asynchronous SRAM in 44-TSOP II — memory selection memo
Housed in a 44-TSOP II package, this volatile memory is a standard choice for high-speed cache, buffer, or working memory in embedded systems where deterministic read/write timing is required.
In a system with a 100 MHz bus, that leaves roughly 10 ns for the memory to respond before the next clock edge — tight but workable with careful PCB trace length matching.
For existing BOM lines, procurement will need to source through independent distribution or consider a pin-compatible alternative in the same family. Both share the same die and timing, so the -10ZSXI can serve as a drop-in replacement for hand-assembly or smaller quantities, though the reel variant is preferred for automated pick-and-place.
The 44-TSOP II (0.400" body width, 10.16 mm) is a common SRAM footprint. If your existing board uses the -10ZSXI (tube/tray), the -10ZSXAT will reflow identically — the only difference is the shipping medium.