15 ns asynchronous SRAM for 3.3 V bus-matched cache
The 44-pin SOJ (Small Outline J-lead) footprint is through-hole compatible on the board edge, common in telecom line cards and industrial controller modules where a socketed or reworkable memory device was preferred.
For BOM lines that depend on this exact footprint and timing, the supply path runs through independent distribution — last-time-buy inventory and surplus stock.
For a 33 MHz bus (30 ns cycle), this leaves a 15 ns margin after the address setup — enough for a typical FPGA or CPLD address decoder without adding pipeline stages. If your controller runs at 50 MHz (20 ns cycle), the 15 ns access time still fits with one wait state, but you lose the zero-wait-state benefit.
It is not specified for industrial enclosures, engine bays, or outdoor cabinets where the ambient regularly exceeds 70°C. If your application sees -40°C or +85°C, you need a different temperature grade variant in the same family.