15 ns asynchronous SRAM for legacy 5V bus designs
It uses a parallel interface and is housed in a 44-TSOP II package. This part targets industrial control, telecom infrastructure, and instrumentation where a fast, 5V-tolerant memory bus is required and the design is already committed to an asynchronous SRAM controller. The 15 ns access time gives the bus a solid timing margin for a 33 MHz to 40 MHz read cycle without wait states.
No production date or last-time-buy window is provided in the record. This part is not available through the factory channel. For new designs, evaluate a current-production asynchronous SRAM family in the same 44-TSOP II footprint, such as the CY7C1021DV33 or ISSI IS61LV1024 series, after verifying supply voltage and timing compatibility.
Package and footprint: 44-TSOP II
The Tape & Reel (TR) delivery option is suited for automated pick-and-place assembly. The part is volatile — data is lost when power is removed, so a backup battery or supercapacitor is required for non-volatile storage.