512Kbit asynchronous SRAM for industrial and automotive cache buffers
It operates from a 2.5V to 2.7V supply rail — narrow enough that a dedicated LDO is the cleanest way to feed it, especially if the board's main 3.3V or 1.8V rail doesn't overlap.
The parallel interface is straightforward to hook up — address, data, chip enable, output enable, and write enable — no clock or refresh overhead. The 2.5V to 2.7V supply means the I/O levels are not 3.3V tolerant; a level shifter or a 2.5V-logic host is needed.
Last Buy — secure stock before the window closes
Once that window shuts, new-manufactured units will no longer be available.
44-TSOP II footprint and storage notes
The 44-TSOP II package (0.400" body width, 10.16 mm) is a standard JEDEC outline shared by many 512Kbit and 1Mbit asynchronous SRAMs, so the board footprint is reusable if you need to qualify a second source.