The CY7C1020B-15ZXCT: No new production is planned; the last-time-buy window has closed. For new designs or BOM sustainment, the part must be sourced from independent inventory or a verified surplus channel.
15 ns access time and 5V-only supply rail
This is a 512Kbit asynchronous SRAM organized as 32K words by 16 bits. The 15 ns access time sets the read-cycle window for the bus master — at 5V nominal, a 15 ns window is tight for legacy 8-bit controllers but comfortable for 16-bit CPLD-based state machines or fast DSPs. The supply range is 4.5V to 5.5V; the part does not operate at 3.3V. The write cycle time matches the read access at 15 ns, so back-to-back writes to the same page incur no extra dead cycles.
44-TSOP II footprint and commercial temperature grade
Housed in a 44-TSOP II package — 0.400-inch body width, 10.16 mm, surface-mount.