Asynchronous SRAM for the 3.3 V bus — 2 Mbit, 10 ns, 128K x 16
It comes in a 44-TSOP II surface-mount package, supplied on Tape & Reel or Cut Tape for production or prototype volumes.
10 ns access time — timing margin on a fast bus
In a system with a 50 MHz or 66 MHz bus clock, a 10 ns read cycle gives roughly one clock period of margin for address decode, data setup, and hold — enough to avoid wait states in most glue-logic designs. If the bus runs faster than 66 MHz, you will need to budget the propagation delay of the address buffers and the FPGA routing before you commit to a no-wait-state path.
Package and supply — what to check on the layout
The 44-TSOP II package (0.400-inch body width, 10.16 mm height) is a standard footprint for asynchronous SRAMs of this density. Decouple with a 0.1 µF ceramic close to each VDD pin; the part draws a few tens of mA in active mode, so a single bulk cap on the board is usually sufficient.
For small quantities or prototype builds, the Cut Tape option is available. For production runs, the Tape & Reel supply is standard. No stock or lead-time figures are published here because the supply picture changes daily; the quickest way to get a firm number is to submit an RFQ.