The CY7C1011CV33-10BAJXE is a 2Mbit asynchronous SRAM from Infineon (formerly Cypress), organized as 128K words by 16 bits. It uses a parallel interface and delivers a 10 ns access time, which sets the timing budget for address-to-data valid on the bus. At 3.3 V nominal (3V to 3.6V range), this part is a drop-in for designs needing fast, simple memory without a clock — no refresh, no setup sequences.
The 10 ns access time is specified across that full range, so timing closure at 125°C uses the same margin as at 25°C. No derating needed for temperature; the part is characterized for it.
Package and supply — layout notes
The 48-TFBGA (6x8 mm) is a fine-pitch ball grid array; the balls are under the package, so routing escapes on a two-layer board are tight — expect to use micro-vias or at least four layers for clean signal routing. Decouple with a 0.1 µF ceramic per supply pin, placed as close to the balls as the layout allows. The write cycle time matches the access time at 10 ns, so back-to-back writes run at the same speed as reads.