12 ns async SRAM in 32-SOJ
The CY7C1009B-12VC is a 1 Mbit asynchronous SRAM organized as 128K x 8 bits, with a 12 ns access time that sets the read-cycle ceiling for the bus it hangs on. Packaged in a 32-SOJ (300 mil body, 7.62 mm width), surface-mount, the J-bend leads make it a candidate for rework with a standard hot-air station — no BGA underfill or X-ray inspection needed. The tube delivery suits low-to-medium volume builds where tray or tape handling isn't justified.
Timing and bus fit
12 ns access time means the SRAM can service a read request within a single 83 MHz clock cycle (12 ns period), or two cycles of a 166 MHz bus. The write cycle time matches at 12 ns — word and page writes complete at the same speed as reads, so no extra wait states for write-back operations. Parallel interface with 8-bit data bus and 17 address lines (A0-A16 for 128K words).
Infineon lists the CY7C1009B-12VC as Obsolete. No official successor part number is recorded — the original 5 V asynchronous SRAM family has been superseded by lower-voltage, higher-density parts with different pinouts. Sourced to order through independent distribution and surplus channels.