15 ns asynchronous SRAM for 5V legacy systems
Packaged in a 28-SOJ (0.300", 7.62mm width) surface-mount package, this part is designed for legacy 5V digital systems requiring fast, simple read/write memory without clocked interfaces.
Obsolete — last-time-buy and surplus channel
For new designs, a current-production asynchronous SRAM in a compatible package and speed grade should be selected.
In a system with a 5V bus running at 33 MHz or slower, this gives enough margin to avoid wait states when the memory controller's address-to-data setup is in the 10–12 ns range.
1M x 1 organization — narrow, deep memory
The 1M x 1 organization means each address accesses a single bit. This is typical for cache tag RAM, deep FIFO buffers, or bit-serial data storage where word width is not needed.
Package and footprint: 28-SOJ
It sits flush on the PCB and is compatible with standard SOJ footprints. The Tape & Reel (TR) packaging is suited for automated pick-and-place assembly.