Dual-port synchronous SRAM — 32K x 36, 6 ns access, 83 MHz
The CY7C09579V-83BBC is a 1.152 Mbit dual-port synchronous SRAM organized as 32K words by 36 bits. The 36-bit word width maps directly to a 32-bit data bus plus parity or ECC lane without external packing logic. Rated for 83 MHz clock operation with a 6 ns access time from clock edge, this part supports back-to-back read/write cycles from either port without wait states when the address and control signals meet setup timing.
Quantities are lot-specific; full traceability and date-code visibility are confirmed at RFQ.
172-FBGA footprint and commercial temp grade
The BGA footprint requires a solder-paste stencil matched to the 0.5 mm ball diameter and a reflow profile per JEDEC J-STD-020 for the package moisture sensitivity level. Suitable for indoor networking equipment, telecom line cards, and industrial controllers that do not see extended or military temperature extremes.