9 ns dual-port synchronous SRAM — what it does for your bus
The Infineon CY7C09369V-9AXCT is a 288Kbit dual-port synchronous SRAM organized as 16K x 18 bits. The 9 ns access time and 67 MHz clock rate mean the part can keep up with a fast local bus without inserting wait states — provided the host controller's memory controller can tolerate the synchronous handshake. Supply runs from 3V to 3.6V, which aligns with a 3.3V logic rail.
Housed in a 100-LQFP (14x14 mm body), the part is a surface-mount device that reflows with standard lead-free profiles. It is not rated for the engine bay or an unventilated enclosure in a factory hall.
Any new design should avoid this part unless you are locked into a legacy board that cannot be re-spun. If you are qualifying a second source for an existing build, look for a pin-compatible dual-port synchronous SRAM in the same 100-LQFP footprint with matching 9 ns access time and 3.3V supply — but verify the bus protocol (synchronous vs asynchronous) and the port arbitration scheme, because not all dual-port SRAMs handle simultaneous writes to the same address the same way.