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Infineon Technologies CY7C09369V-6AXC — Memory (DRAM / SRAM / Flash / EEPROM)

Infineon CY7C09369V-6AXC SRAM, 288Kbit, 6.5 ns, 100 MHz

MPNCY7C09369V-6AXC
Obsolete

Infineon CY7C09369V-6AXC synchronous dual-port SRAM, 288Kbit (16K x 18), 6.5 ns access time, 100 MHz clock, 3V–3.6V supply, 100-TQFP, commercial temperature.

$67.6700Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C09369V-6AXC specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Voltage3V ~ 3.6V
Frequency100 MHz
Memory interfaceParallel
Operating temperature0°C ~ 70°C (TA)
PackageTray
TechnologySRAM - Dual Port, Synchronous
Access time6.5 ns
Memory size288Kbit
Memory formatSRAM
Case100-LQFP
Memory organization16K x 18

Product details

The Infineon CY7C09369V-6AXC is a 288Kbit synchronous dual-port SRAM organized as 16K x 18, with a 6.5 ns access time and a 100 MHz clock. The 18-bit word width is the key differentiator here: the extra two bits per word let you carry a parity or ECC check bit alongside the 16-bit data path, which is exactly what you want in a shared-memory buffer where data integrity matters — think base-station line cards, video frame buffers, or multiprocessor mailboxes. The 6.5 ns access time means the part can keep up with a 100 MHz bus without inserting wait states, provided the controller's output hold time and the PCB trace delay budget are within a couple of nanoseconds.

Obsolete — no official replacement on record

The CY7C09369V-6AXC is Obsolete. No official successor is listed. A replacement would need to match the 16K x 18 organization, 6.5 ns access time, 100 MHz clock, 3V~3.6V supply, and 100-LQFP footprint.

100-TQFP footprint and commercial temperature grade

The part comes in a 100-LQFP package, surface-mount, supplied in Tray. It is intended for indoor, temperature-controlled environments.

Frequently asked questions

What is the memory organization of CY7C09369V-6AXC?

It is organized as 16K x 18 bits — 288Kbit total. The 18-bit word width supports parity or ECC alongside a 16-bit data bus.