Synchronous dual-port SRAM — 9 ns arbitration
The Infineon CY7C09289V-9AC is a 1 Mbit synchronous dual-port SRAM organized as 64K words by 16 bits. It provides two independent ports with separate address, data, and control buses, allowing simultaneous read/write access from two bus masters without dead cycles. The 9 ns access time and 67 MHz clock rate support back-to-back transactions with zero wait states in shared-memory applications such as multi-processor buffers, video frame stores, and network packet queues. Operating from a 3 V to 3.6 V supply, it comes in a 100-pin TQFP (14x14 mm) surface-mount package and is rated for commercial temperature range (0°C to 70°C).
9 ns access — bus timing margin
The 9 ns access time is the time from address assertion to valid data on the bus. In a 67 MHz synchronous system, this leaves setup/hold margin after accounting for clock-to-output delay and board trace skew.