1.152 Mbit dual-port synchronous SRAM — 9 ns access, 67 MHz clock
The Infineon CY7C09199V-9AXI is a 1.152 Mbit synchronous dual-port SRAM organized as 128K x 9 bits. It provides two independent ports with separate address, data, and control lines, allowing simultaneous read/write access from two bus masters — essential for shared-memory arbitration in multiprocessor systems, network switches, and telecom line cards. The 9 ns access time and 67 MHz clock rate support back-to-back transactions with zero dead cycles, matching the throughput demands of high-speed FIFO buffers and packet-processing engines.
Package and footprint — 100-TQFP (14x14)
Lifecycle status — obsolete, no direct successor on record
For new designs, evaluate current dual-port SRAMs after verifying pin compatibility and timing.
