576Kbit synchronous dual-port SRAM — 9 ns access, 67 MHz arbitration
The Cypress CY7C09189-9AC is a 576Kbit synchronous dual-port SRAM organized as 64K x 9 bits. It provides two independent ports with separate address, data, and control lines, allowing simultaneous read/write access from two bus masters or processors. The 9 ns access time and 67 MHz clock frequency support high-speed arbitration in multiprocessor or shared-memory systems without dead cycles.
9 ns access time — timing margin for dual-port arbitration
In a synchronous dual-port design, this rating directly affects the timing closure for read/write cycles when both ports contend for the same memory location. A 9 ns window leaves comfortable margin for a 67 MHz clock period (14.9 ns), provided board traces are kept short and decoupling is adequate. The synchronous architecture eliminates the bus-turnaround dead cycles typical of asynchronous dual-port SRAM, so back-to-back throughput can approach the clock rate.
Obsolete — last-time-buy and sourcing reality
The CY7C09189-9AC is officially obsolete per the manufacturer's lifecycle status. This is not a part to qualify into a new design; it is a legacy fill for existing boards.