The Infineon CY7C09089V-6AXC is a 512Kbit synchronous dual-port SRAM organized as 64K x 8 bits. It provides two independent ports with separate address, data, and control lines, allowing simultaneous read/write access from two bus masters — a common architecture for shared-memory buffers in DSP-to-FPGA links, multiprocessor mailboxes, or high-speed data acquisition front-ends. The 6.5 ns access time and 100 MHz clock frequency mean this part can sustain back-to-back pipelined reads or writes without wait states on a 100 MHz bus — critical for timing closure in tight signal-integrity budgets. The parallel interface is byte-wide. Packaged in a 100-LQFP (14x14 mm), surface-mount only.
The CY7C09089V-6AXC is officially obsolete per Infineon's product status. No direct pin-compatible replacement has been announced under the CY7C09089 base number. The date-code and marking traceability are verified before shipment; the laser etch and package consistency are checked against Infineon's known factory patterns.
What the 6.5 ns access time means for your bus
At 6.5 ns access and 100 MHz clock, the part delivers pipelined reads without wait states. The synchronous pipeline eliminates the dead-cycle penalty of asynchronous dual-port SRAMs on back-to-back reads.