Dual-port synchronous SRAM for shared-memory architectures
The CY7C0832AV-167AXC is a 4.5 Mbit dual-port synchronous SRAM organized as 256K words by 18 bits, clocked at 167 MHz over a parallel interface. Dual-port architecture means two independent buses can read from or write to the memory array simultaneously — the arbitration logic on-chip resolves contention when both ports access the same address in the same cycle. The 18-bit word width (16 data + 2 parity or byte-control bits) suits it for shared-buffer designs in network switches, baseband processors, and multi-core DSP systems where two agents need low-latency access to a common pool.
Supplied in tray format, which is the standard carrier for LQFP packages through assembly and test — no reel or tape-and-reel option is listed for this variant.
Lifecycle reality — obsolete, sourced through surplus channels
Availability is limited to independent-distribution surplus and broker inventory.