20 ns access time — dual-port arbitration ceiling
The CY7C036AV-20AC is a 288Kbit dual-port asynchronous SRAM with a 20 ns access time and a matching 20 ns write cycle time. In a dual-port architecture, the 20 ns window sets the latency for both read and write operations when both ports contend for the same memory location — the arbitration logic resolves the collision, but the access time governs how quickly the bus releases for the next transaction.
16K × 18 organization — why the 18-bit word matters
Organized as 16K words of 18 bits each, this SRAM stores an extra bit per byte beyond the standard 16-bit width. The 18th bit is commonly used for parity storage in data-path applications — a DSP or FPGA reading a 16-bit word plus parity can detect single-bit errors without external logic.
Infineon Technologies lists the CY7C036AV-20AC as obsolete. No official successor or pin-compatible replacement is recorded. For a BOM line that requires this exact dual-port SRAM, the procurement path is last-time-buy inventory management — no direct factory order is possible.
100-TQFP — board integration notes
Supplied in a 100-LQFP package (also designated 100-TQFP, 14x14 mm body). The fine-pitch leads demand a controlled reflow profile — the package moisture sensitivity level should be verified before the board enters the oven. The commercial temperature range (0°C to 70°C) limits deployment to indoor, temperature-controlled environments; no industrial or automotive ambient is supported.