The Infineon CY7C028V-20AXCT is a 1Mbit dual-port asynchronous SRAM organized as 64K x 16, built for systems where two independent processors or controllers need simultaneous access to a shared memory block without bus contention. The 20 ns access time keeps read/write cycles tight enough for moderate-speed DSP handshakes, FIFO emulation, or mailbox registers in telecom line cards and industrial controllers. The parallel interface and 3V to 3.6V supply align with 3.3V logic families common in late-2000s embedded designs.
20 ns access time — timing closure for the bus
The 20 ns access time is the window from address assertion to valid data on the bus. In a dual-port scenario, both ports run independently at that speed, so the system must budget for arbitration logic delay plus the SRAM's own access time when sizing the memory cycle.
Infineon (formerly Cypress) has ended production; no last-time-buy window remains open.
Package and footprint — 100-TQFP on Tape & Reel
The Tape & Reel (TR) packaging option suits automated pick-and-place lines. The supplier device package is 100-TQFP (14x14) — the same mechanical footprint as the broader CY7C028 family, so a board laid out for the -20AXC or -20AXI industrial variant will take this part without a layout change, provided the temperature grade is acceptable.