Dual-port SRAM for shared-memory arbitration
The CY7C028V-15AXCT: Two independent ports allow simultaneous read/write access from separate bus masters — a common architecture for shared memory in multi-processor systems, FIFO buffers, or bridge controllers where one side writes while the other reads without wait-state arbitration logic.
A 15 ns access time means the SRAM presents valid data on the bus within 15 ns of the address being latched — fast enough to keep pace with a 66 MHz bus clock without inserting wait states. The write cycle time matches at 15 ns, so back-to-back writes at the same rate are supported. The 100-TQFP package (14×14 mm body) has a 0.5 mm pitch — a four-layer board with via-in-pad or microvias is the practical fan-out for the inner rows.
Infineon lists the CY7C028V-15AXCT as Obsolete. No second-source cross-reference is maintained.