The Infineon CY7C028AV-25AXC is a 1 Mbit dual-port asynchronous SRAM organized as 64K x 16 bits. It gives two independent processors or controllers simultaneous access to a common memory array through separate left and right port buses, each with its own address, data, and control lines. This part is built for shared-buffer applications like baseband processors, video frame buffers, or multiprocessor mailboxes where the two sides exchange data without a serial bottleneck.
25 ns access — timing margin in a dual-port system
In a system running a 40 MHz bus clock (25 ns period), that leaves zero margin for address decoding and PCB trace delay — the bus must be designed for zero-wait-state operation at that speed. If the other side of the dual-port is a slower peripheral, the 25 ns spec still sets the minimum cycle time for back-to-back reads. For designs that need headroom, the -20AXC speed grade (20 ns) exists, but the -25AXC is the more common, cost-optimized variant for 33 MHz or slower buses.
New-stock procurement now runs through independent distribution and surplus channels. No direct factory replacement has been announced for this exact speed grade; the CY7C028 family shares the same footprint and pinout across speed bins, so a -20AXC or -25AXI variant may serve as a drop-in if the system can tolerate the timing or temperature difference, but those are also end-of-life. For a new design, consider a current-generation dual-port SRAM from Infineon or a serial-memory alternative with an FPGA bridge.