The Infineon CY7C026A-20AC is a 256 Kbit asynchronous dual-port SRAM organized as 16K x 16, with a 20 ns access time that sets the bus turnaround window when two controllers or processors share a memory block. The dual-port architecture gives each port independent address, data, and control lines, so both sides can read or write simultaneously unless they hit the same address — arbitration logic on-chip handles that collision. Typical applications include shared memory in multi-processor systems, FIFO buffers in telecom line cards, and data-exchange mailboxes in industrial controllers where the two sides run on separate clocks.
The 20 ns access time and matching 20 ns write cycle time mean the part can keep up with a 50 MHz bus without wait states, assuming the controller's output hold and setup windows fit. That timing is tight enough for most 5 V tolerant CPLD or FPGA interfaces, but if you are pairing it with a faster ASIC that expects 12 ns or 15 ns, you will need to add wait states or switch to a faster dual-port.
Not suitable for outdoor, under-hood, or unheated enclosures where the temperature dips below freezing or climbs above 70°C.
Supplied in a 100-pin LQFP with a 14 mm x 14 mm body, surface-mount only.
RoHS non-compliant — BOM flag
The CY7C026A-20AC is listed as RoHS non-compliant. If your BOM requires RoHS compliance, you will need to source a lead-free variant or an alternate dual-port SRAM.