Dual-port SRAM for shared-memory handoff — 20 ns access keeps the bus moving
The Infineon CY7C025AV-20AC is a 128Kbit asynchronous dual-port SRAM organized as 8K x 16, designed for systems where two independent bus masters — two processors, a DSP and an MCU, or a controller and an FPGA — need to exchange data without arbitration latency. The 20 ns access time means a read or write completes in one fast cycle at typical 50 MHz bus speeds, so neither port stalls the other. Supply runs from 3V to 3.6V, making it a fit for 3.3 V logic families common in mid-2000s embedded designs. The 100-TQFP (14x14) package is the surface-mount footprint for that generation of shared-memory applications.
Obsolete — plan for surplus or replacement now
Infineon lists the CY7C025AV-20AC as obsolete. For new production or repair, the only channel is independent distribution — surplus inventory, new-old-stock, or broker-sourced lots. If you are qualifying a BOM line, verify the 100-TQFP footprint and 20 ns timing against any candidate replacement; a same-function dual-port SRAM from a different vendor may require a timing or supply-voltage adjustment.
At a 50 MHz bus clock (20 ns period), a single wait-state gives the memory a full cycle to respond; with a 0-wait controller the 20 ns part must meet the setup time at the receiving flip-flop, which usually closes timing. If your system runs a slower bus (say 25 MHz or below), the 20 ns part provides comfortable margin; if you are pushing toward 66 MHz, you would need a 12 ns or 10 ns dual-port SRAM.