25 ns dual-port SRAM for shared-memory arbitration
The CY7C025-25JXI is a 128Kbit asynchronous dual-port SRAM organized as 8K x 16 bits, with a 25 ns access time that sets the arbitration window for two independent bus masters reading or writing the same memory array without dead cycles. Running on a 4.5V to 5.5V supply, it fits legacy 5 V logic environments where a voltage translation step would add latency or cost.
Industrial temperature grade and 84-PLCC package
The 84-lead PLCC with J-leads (29.31 mm body) is a surface-mount package that reflows well with a standard hot-air profile — the J-lead gives a visible solder joint for inspection, unlike a QFN or BGA.
Infineon lists the CY7C025-25JXI as Obsolete, meaning no new production runs. The only available units are existing stock held by distributors or on the open market.