PLL clock distribution in a 32-PLCC package
The Cypress CY7B991-2JCT is a PLL-based clock buffer from the RoboClock series, combining fanout distribution and zero-delay buffering in a 32-lead PLCC package. It accepts one CMOS input and delivers eight CMOS outputs, with a maximum operating frequency of 80 MHz. The internal PLL aligns output edges to the input, eliminating propagation delay across the clock tree — useful for synchronising multiple loads on a single board.
5V supply and commercial temperature range
The single-circuit design handles one PLL domain; for multiple independent clock domains you would need additional instances.
No last-time-buy window is in effect. The part is RoHS non-compliant, so verify your assembly line's solder alloy compatibility if you are migrating to lead-free.
Rework and footprint notes
The 32-lead PLCC package uses J-leads, which are hand-reworkable with a hot-air station — the leads are visible and accessible. The body measures 11.43 x 13.97 mm. This footprint is not compatible with SOIC or QFP patterns, so a dedicated PLCC socket or land pattern is required.