4 Mbit asynchronous SRAM in 44-TSOP II
The Infineon CY62146ESL-45ZSXIT is a 4 Mbit asynchronous SRAM organized as 256K x 16 bits, part of the MoBL® series. The 45 ns access time sets the read-cycle ceiling for the parallel bus — the processor must insert wait states if its bus clock period is shorter than the sum of access time, setup, and hold. The Tape & Reel variant (TR) is the standard pick-and-place feed; the Cut Tape (CT) option supports prototype or low-volume builds without committing to a full reel.
Supply voltage and temperature grade
Write cycle time matches the read access at 45 ns (word, page mode), so the bus timing is symmetrical — no extra wait states on writes versus reads. The parallel interface is straightforward: address, data, chip enable, output enable, and write enable lines connect directly to the host controller.