Async SRAM for low-power embedded memory
The Infineon CY62146DV30LL-70ZSI is a 4 Mbit asynchronous SRAM organized as 256 K x 16, operating from a 2.2 V to 3.6 V core supply. The 70 ns access time sets the read/write cycle ceiling for the bus — the SoC must hold the address stable for at least that window, and the data bus floats until the output enable asserts. This is a MoBL (More Battery Life) device, optimized for standby current in battery-backed or low-power systems.
Active production and sourcing posture
Infineon lists the CY62146DV30LL-70ZSI as Active (current product status per).
Package and board-level integration
The 70 ns speed grade and 3.0 V nominal rail align with common MCU memory bus interfaces; the output enable and chip enable pins allow the bus to tristate when the SRAM is not selected, reducing contention on shared data lines.