128K x 16 word width — matches 16-bit data buses without byte packing
The CY62136CV30LL-70BVI: The 2 Mbit SRAM is organized as 128K words of 16 bits each, so a 16-bit microcontroller or DSP reads and writes the full word in one cycle — no byte-lane shift or two-cycle packing needed. 70 ns access time and 70 ns write cycle time set the bus timing margin for the parallel interface; at a 14 MHz bus clock the SRAM meets zero-wait-state operation with a 10 ns hold budget.
Supply and temperature — single-rail industrial part
48-VFBGA (6x8 mm) fine-pitch BGA — the 0.75 mm ball pitch demands a 4-layer PCB with via-in-pad or microvia fan-out; two-layer boards cannot route the inner balls.
Active lifecycle, RoHS non-compliant — legacy BOM only
No successor part number has been published, so this remains the current order code for the 128K x 16 MoBL SRAM in this package. RoHS non-compliant — the die attach or lead finish contains lead. This part fits legacy BOMs that are exempt from RoHS or have a blanket waiver. For RoHS-compliant builds, Infineon offers the CY62136CV30LL-70BVXI (same specs, RoHS-compliant finish).