5V asynchronous SRAM for harsh environments
The Infineon CY62128ELL-55SXE is a 1 Mbit asynchronous SRAM from the MoBL® family, organized as 128K x 8 bits.
A 55 ns access time means the SRAM can complete a read or write cycle in 55 ns from address assertion. This is a relaxed timing compared to modern 10 ns or 12 ns parts, but it is intentionally matched to slower microcontrollers (e.g., 8-bit or 16-bit MCUs running below 20 MHz) or to systems where the bus timing is already gated by other peripherals. For a legacy 8051 or a ColdFire bus running at 8–12 MHz, the 55 ns window is comfortable.
Industrial temperature and 5V rail
If your design migrated to 3.3V, look at the 3V MoBL variants (e.g., CY7C1018DV33) which are pin-compatible but operate at 3.0V to 3.6V. The 32-SOIC (300-mil wide) footprint is common and socket-friendly for prototyping.